`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:27:37 03/31/2014
// Design Name:   TOP
// Module Name:   X:/EC551/proj_ex_3/test_all.v
// Project Name:  proj_ex_3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: TOP
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_all;

	// Inputs
	reg clk = 0;
	reg reset = 0;
	reg resume_button = 0;

	// Outputs
	wire [7:0] R0;
	wire [7:0] R1;
	wire [7:0] R2;
	wire [7:0] R3;
	wire [7:0] R4;
	wire [7:0] R5;
	wire [7:0] R6;
	wire [7:0] R7;
	wire [11:0] pc;
	wire [1:0] cmp_flag;
	wire vid_line;
	wire [3:0] aud_line;
	wire [3:0] poll_line;

	// Instantiate the Unit Under Test (UUT)
	TOP uut (
		.R0(R0), 
		.R1(R1), 
		.R2(R2), 
		.R3(R3), 
		.R4(R4), 
		.R5(R5), 
		.R6(R6), 
		.R7(R7), 
		.pc(pc), 
		.cmp_flag(cmp_flag), 
		.vid_line(vid_line), 
		.aud_line(aud_line), 
		.poll_line(poll_line), 
		.clk(clk), 
		.reset(reset), 
		.resume_button(resume_button)
	);

	initial begin
		// Initialize Inputs
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk; reset = 1'b1;
		#20 clk = ~clk;
		#20 clk = ~clk; reset = ~reset;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		#20 clk = ~clk;
		

	end
      
endmodule

